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RM0008
Figure 125. Capture/compare channel 1 main circuit
APB Bus
MCU-peripheral interface
General-purpose timer (TIMx)
8
8
read CCR1H S
read CCR1L
R
read_in_progress
write_in_progress
Capture/Compare Preload Register
output
capture_transfer c ompare_transfer mode
S write CCR1H
write CCR1L
R
CC1S[1]
CC1S[0]
CC1S[1]
CC1S[0]
IC1PS
input
mode
Capture/Compare Shadow Register
capture
comparator
OC1PE
OC1PE
UEV
TIMx_CCMR1
(from time
base unit)
CC1E
CNT>CCR1
CC1G
Counter
CNT=CCR1
TIMx_EGR
Figure 126. Output stage of capture/compare channel (channel 1)
ETRF
To the master mode
controller
0
Output
OC1
Enable
1
Circuit
CNT > CCR1
Output Mode oc1ref
CNT = CCR1 Controller
CC1P
TIMx_CCER
CC1E TIMx_CCER
OC1M[2:0]
TIMx_CCMR1
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
Doc ID 13902 Rev 9
335/995
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